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CD4029BC Presettable Binary/Decade Up/Down Counter
October 1987 Revised January 1999
CD4029BC Presettable Binary/Decade Up/Down Counter
General Description
The CD4029BC is a presettable up/down counter which counts in either binary or decade mode depending on the voltage level applied at binary/decade input. When binary/ decade is at logical "1", the counter counts in binary, otherwise it counts in decade. Similarly, the counter counts up when the up/down input is at logical "1" and vice versa. A logical "1" preset enable signal allows information at the "jam" inputs to preset the counter to any state asynchronously with the clock. The counter is advanced one count at the positive-going edge of the clock if the carry in and preset enable inputs are at logical "0". Advancement is inhibited when either or both of these two inputs is at logical "1". The carry out signal is normally at logical "1" state and goes to logical "0" state when the counter reaches its maximum count in the "up" mode or the minimum count in the "down" mode provided the carry input is at logical "0" state. All inputs are protected against static discharge by diode clamps to both VDD and VSS.
Features
s Wide supply voltage range: s High noise immunity: s Low power TTL compatibility: or 1 driving 74LS s Parallel jam inputs s Binary or BCD decade up/down counting 3V to 15V fan out of 2 driving 74L 0.45 VDD (typ.)
Ordering Code:
Order Number CD4029BCWM CD4029BCSJ CD4029BCN Package Number M16B M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide body 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC and SOP
Top View
(c) 1999 Fairchild Semiconductor Corporation
DS005960.prf
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CD4029BC
Logic Diagram
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CD4029BC
Absolute Maximum Ratings(Note 1)
(Note 2) DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) 260C (Note 2) 700 mW 500 mW -0.5V to +18 VDC -0.5V to VDD + 0.5 VDC -65C to +150C
Recommended Operating Conditions (Note 2)
DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) 3V to 15 VDC 0V to VDD VDC -40C to +85C
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation. Note 2: VSS = 0V unless otherwise specified.
DC Electrical Characteristics
Symbol IDD Parameter Quiescent Device Current VDD = 5V VDD = 10V VDD = 15V VOL LOW Level Output Voltage |IO| < 1 A VDD = 5V VDD = 10V VDD = 15V VOH HIGH Level Output Voltage |IO| < 1 A VDD = 5V VDD = 10V VDD = 15V VIL LOW Level Input Voltage VIH HIGH Level Input Voltage IOL LOW Level Output Current (Note 3) IOH HIGH Level Output Current (Note 3) IIN Input Current
Conditions
-40C Min Max 20 40 80 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.52 1.3 3.6 -0.52 -1.3 -3.6 -0.3 0.3 3.5 7.0 11.0 0.44 1.1 3.0 -0.44 -1.1 -3.0 4.95 9.95 14.95 Min
+25C Typ Max 20 40 80 0 0 0 5 10 15 1.5 3.0 4.0 0.05 0.05 0.05
+85C Min Max 150 300 600 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0
Units A A A V V V V V V V V V V V V mA mA mA mA mA mA
VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1V or 9V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1V or 9V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.4V VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V VDD = 5V, VO = 4.6V VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V
0.88 2.25 8.8 -0.88 -2.25 -8.8 -10-5 10-5 -0.3 0.3
0.36 0.9 2.4 -0.36 -0.9 -2.4 -1.0 1.0
A A
Note 3: IOH and IOL are tested one output at a time.
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CD4029BC
AC Electrical Characteristics
Symbol CLOCKED OPERATION tPHL or tPLH Propagation Delay Time to Q Outputs tPHL or tPLH Propagation Delay Time to Carry Output tPHL or tPLH Propagation Delay Time to Carry Output Parameter
(Note 4)
Conditions VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V CL = 15 pF VDD = 5V VDD = 10V VDD = 15V 285 120 95 100 50 40 160 70 55 15 10 5 180 70 55 1.5 3.7 4.5 3.1 7.4 9 5 65 285 115 95 400 165 135 80 30 25 150 60 50 265 110 90 200 85 70 570 230 195 800 330 260 160 60 50 300 120 100 530 220 180 400 170 140 7.5 360 140 110 570 240 190 200 100 80 320 135 110 ns ns ns ns ns ns ns ns ns s s s ns ns ns MHz MHz MHz pF pF ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min Typ Max Units
TA = 25C, CL = 50 pF, RL = 200k, Input trCL = tfCL = 20 ns, unless otherwise specified
200 85 70 320 135 110
400 170 140 640 270 220
ns ns ns ns ns ns
tTHL or tTLH
Transition Time/Q or Carry Output
VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V
tWH or tWL
Minimum Clock Pulse Width
trCL or tfCL
Maximum Clock Rise and Fall Time
tSU
Minimum Set-Up Time
fCL
Maximum Clock Frequency
VDD = 5V VDD = 10V VDD = 15V
CIN CPD tPHL or tPLH
Average Input Capacitance Power Dissipation Capacitance Propagation Delay Time to Q output
Any Input Per Package (Note 5) VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V
PRESET ENABLE OPERATION
tPHL or tPLH
Propagation Delay Time to Carry Output
tWH
Minimum Preset Enable Pulse Width
tREM
Minimum Preset Enable Removal Time
CARRY INPUT OPERATION tPHL or tPLH Propagation Delay Time to Carry Output tPHL, tPLH Propagation Delay Time to Carry Output VDD = 5V VDD = 10V VDD = 15V CL = 15 pF VDD = 5V VDD = 10V VDD = 15V
Note 4: *AC Parameters are guaranteed by DC correlated testing. Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application note, AN-90.
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CD4029BC
Logic Waveforms
Decade Mode
Binary Mode
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CD4029BC
Switching Time Waveforms
Cascading Packages
Parallel Clocking
Ripple Clocking
Carry out lines at the 2nd or later stages may have a negative-going spike due to differential internal delays. These spikes do not affect counter operation, but if the carry out is used to trigger external circuitry the carry out should be gated with the clock.
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CD4029BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body Package Number M16B
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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CD4029BC Presettable Binary/Decade Up/Down Counter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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